1. Field of the Invention
The present invention relates to semiconductor integrated circuit structures, and more particularly to an off-chip driver circuit for integrated circuits.
2. Background Art
U.S. Pat. No. 5,654,663 issued Aug. 5, 1997 to McClure et al. entitled CIRCUIT FOR PROVIDING A COMPENSATED BIAS VOLTAGE discloses a bias circuit for generating a bias voltage for a power supply voltage that comprises a voltage divider to generate a divided voltage based on a power supply value. The divided voltage is applied to a current mirror device which controls a current applied to a linear load device. The voltage across the load device determines the bias voltage.
U.S. Pat. No. 5,640,122 issued Jun. 17, 1997 to McClure entitled CIRCUIT FOR PROVIDING A BIAS VOLTAGE COMPENSATED FOR P-CHANNEL TRANSISTOR VARIATIONS discloses a bias circuit for generating a bias voltage that tracks power supply voltage variations that comprises a voltage divider to produce a ratioed voltage based on the power supply voltage to be tracked.
U.S. Pat. No. 5,581,197 issued Dec. 3, 1996 to Motley et al. entitled METHOD OF PROGRAMMING A DESIRED SOURCE RESISTANCE FOR A DRIVER STAGE discloses an output impedance in a CMOS output driver stage that is programmed and compensated by complementary current mirrors that are MOS devices in series with each of the conventional pull-up and pull-down devices.
U.S. Pat. No. 5,568,084 issued Oct. 22, 1996 to McClure et al. entitled CIRCUIT FOR PROVIDING A COMPENSATED BIAS VOLTAGE discloses a bias circuit for generating a bias voltage for a power supply voltage that comprises a voltage divider to generate a divided voltage based on a power supply value. The divided voltage is applied to a current mirror device which controls a current applied to a linear load device. The voltage across the load device determines the bias voltage.
U.S. Pat. No. 4,533,839 issued Aug. 6, 1985 to Balakrishnan entitled CURENT LIMITING CIRCUIT FOR HIGH CURRENT PERIPERAL DRIVERS discloses a driver circuit including a switching output transistor operated from a digital logic control and provided with a shut off circuit which turns the output transistor off when its collector supply current exceeds its saturation current.
U.S. Pat. No. 5,455,522 issued Oct. 3, 1995 to Jones entitled PROGRAMMABLE LOGIC OUTPUT DRIVER discloses a programmable logic output driver circuit that comprises a bias generator, a current mirror, an output stage and a programming feature to maintain the output voltage slew rate at an acceptable value for either high or low values of load capacitances.
U.S. Pat. No. 5,428,303 issued Jun. 27, 1995 to Pasqualini entitled BIAS GENERATOR FOR LOW GROUND BOUNCE OUTPUT DRIVER discloses a bias generator that includes a bias control signal generator, a current difference circuit with a resistive divider and a down current mirror that drives a final pull-down transistor of an output driver circuit.